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The Back-End Maverick: How Packaging Is Revolutionizing Semis

A CPU going into a motherboard, carefully placed by gloved hands and utilizing cutting-edge semiconductor technology.
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The TD Cowen Insight

The technical limits of Moore’s Law, which posited that the number of transistors on a semiconductor doubles every two years, are being tested. This is happening just as far more sophisticated and demanding chips for AI applications require more processing power. Advanced packaging is attempting to fill that void. This report explores how investors should capitalize on this long-term industry trend.

What is Moore’s Law?

In 1965, Gordon Moore, the co-founder of Fairchild Semiconductor and Intel, posited that the number of transistors in an integrated circuit doubles about every two years. “Moore’s Law,” as it became known, was a truism for decades. For years, the source of differentiation in the semiconductor industry was in the “front end” – designing and fabricating wafers to take advantage of Moore’s Law – while “back-end” processes were usually outsourced to semiconductor assembly and test companies (OSATs). These OSATs competed on manufacturing costs rather than technological differentiation. However, node advancement, which dictates the number of features a chip can have (such as transistor density), is reaching its limits.

How Does Advanced Packaging Improve Chip Manufacturing

Technical advances on the front end of chip manufacturing are slowing. Advanced packaging technologies, such as “system on a chip,” are now trying to fill the void. Advanced packaging are far more sophisticated packaging processes that aggregate components from various wafers and create a single electronic device with superior performance. Although the underlying technology of advanced packaging has been around for several decades, the criticality of advanced packaging has been heightened recently as far more sophisticated chips for AI applications emerge.

The Debate Surrounding Advanced Packaging Die Bonding Equipment

The most significant debate within advanced packaging centers on what the dominant die bonding equipment type will be over the next five years. Die bonding, which involves bonding chips to create larger packages, typically occurs during the latter manufacturing stages (back-end). The market is uncertain whether thermos compression bonding or hybrid bonding tools will prevail in the advanced die bonding equipment industry. The consensus view is more optimistic about HB. We believe hybrid bonding makes sense in the long term, but we see a more prominent role for thermos compression bonding in the intermediate term. This favors thermos compression bonding equipment manufacturers.

Overview of Advanced Packaging Technologies

Our report provides an in-depth overview of different advanced packaging technologies, and how the anticipated uptake of each affects our stock coverage universe. Additionally, we highlight bottleneck areas in ramping CoWoS capacity used in GPUs, the chips critical to emerging advanced applications such as AI (CoWoS refers to chipon-wafer-on-substrate, one of the more important packaging techniques being advanced).

Forecasting Semiconductor Manufacturing Revenue

We see technologies such as CoWoS, and high bandwidth memory (HBM) driving more than $5 billion in semiconductor manufacturing revenue (WFE) by 2026. Given the low utilization levels across foundry and memory today, many customers are reusing existing tools to support their packaging investments. This factors into limiting the near-term benefit.

We believe this is not sustainable as for every 1 HBM bit created through upgrades, 3 double data rate (DDR) bits are taken out from supply. So, once greenfield investments resume (C25 base case), we expect investors to be able to assess the benefits from packaging and HBM on WFE. Also, as noted, we expect thermo-compression bonding to take share from the ~$500M Flip Chip Mass Reflow market.

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